Resistance variable memory elements, which include memory elements using chalcogenide glasses, have been investigated for suitability as semi-volatile and non-volatile random access memory devices. An exemplary chalcogenide resistance variable memory element is disclosed in U.S. Pat. No. 6,867,064 to Campbell et al.
In a typical chalcogenide resistance variable memory element, a conductive material, for example, silver or copper, is incorporated into a chalcogenide glass. The resistance of the chalcogenide glass can be programmed to stable higher resistance and lower resistance states. An unprogrammed chalcogenide variable resistance memory element is normally in a higher resistance state. A write operation programs the element to a lower resistance state by applying a voltage potential across the chalcogenide glass and forming a conductive pathway therein. The element may then be read by applying a voltage pulse of a lesser magnitude than the magnitude required to program the element; the resistance across the memory device is then sensed as higher or lower to define two logic states.
The programmed lower resistance state of a chalcogenide variable resistance element can remain intact for an indefinite period, typically ranging from hours to weeks, after the voltage potentials are removed; however, some refreshing may be useful. The element can be returned to its higher resistance state by applying a reverse voltage potential of about the same order of magnitude as used to write the device to the lower resistance state. Again, the higher resistance state is maintained in a semi- or non-volatile manner once the voltage potential is removed. In this way, such an element can function as a semi- or non-volatile variable resistance memory having at least two resistance states, which can define two respective logic states, i.e., at least a bit of data.
FIG. 1 illustrates an exemplary construction of a resistance variable memory element 10 and an access transistor 83, as described in U.S. Pat. No. 6,867,064. The memory element 10 is fabricated over a semiconductor substrate 62 and comprises a first insulating layer 60 formed over the substrate 62. The insulating layer 60 contains a conductive plug 61. A first metal electrode 52 is formed within a second insulating layer 53 provided over the insulating layer 60 and plug 61. A third insulating layer 68 is formed over the first electrode 52 and second insulating layer 53. A chalcogenide glass layer 58 is within the third insulating layer 68. A metal, such as silver, is incorporated into the chalcogenide glass layer 58.
As shown in FIG. 1, the first electrode 52 is electrically connected to a source/drain region 81 of an access transistor 83, which is fabricated within and on the substrate 62. Another source/drain region 85 is connected by a bit line plug 87 to a bit line of a memory array. For purposes of clarity, the bit lines and word lines are not shown in FIG. 1. The gate of the transistor 83 is part of a word line which is connected to a plurality of resistance variable memory elements just as a bit line (not shown) may be coupled to a plurality of resistance variable memory elements through respective access transistors. The bit line may be formed over a fourth insulating layer (not shown) and connects to the bit line plug 87, which in turn connects to access transistor 83 as described above.
One of the limiting factors in increasing the density of a memory device array is the amount of substrate 62 surface area used to form each memory element 10 and associated devices, such as the access transistor 83. In the industry terminology, the surface area required for a memory cell is characterized in terms of the minimum feature size “F” that is obtainable by the lithography technology used to form the memory cell. As shown in FIG. 1, the conventional memory element 10 is laid out with an access transistor 83 that includes first and second source/drain regions 83, 85 that are disposed horizontally along the substrate 62 surface. When isolation between adjacent transistors is considered, the surface area required for such a transistor is generally 8F2 or 6F2.
Accordingly, there is a need in the art for resistance variable memory devices having more efficient use of substrate surface.